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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:31:53 10/03/2013 
-- Design Name: 
-- Module Name:    mux_gen_4_wide - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux_gen_4_wide is
	generic (bus_size : integer := 32);
	PORT (
	i0 : in STD_LOGIC_VECTOR(bus_size-1 downto 0);
	i1 : in STD_LOGIC_VECTOR(bus_size-1 downto 0);
	i2 : in STD_LOGIC_VECTOR(bus_size-1 downto 0);
	i3 : in STD_LOGIC_VECTOR(bus_size-1 downto 0);
	
	selector : in STD_LOGIC_VECTOR(1 downto 0);
	output : out STD_LOGIC_VECTOR(bus_size-1 downto 0);
	neg : in STD_LOGIC
	);
	
end mux_gen_4_wide;

architecture Behavioral of mux_gen_4_wide is
	
begin
	
	process(i0, i1, i2, i3, selector)
	begin
		case selector is 
         when "00" => output <= i0 xor (15 downto 0 => (i1(15) and neg));
         when "01" => output <= i1 xor (15 downto 0 => (i1(15) and neg));
         when "10" => output <= i2 xor (15 downto 0 => (i3(15) and neg));
         when "11" => output <= i3 xor (15 downto 0 => (i3(15) and neg));
         when others => output <= i0;
      end case;
	end process;

end Behavioral;

